In a high speed fully differential switched capacitor filter architecture, a main differential amplifier loop usually includes a high speed common mode loop amplifier within the main differential loop amplifier. A block diagram of a fully differential operational amplifier with common mode feedback is shown in FIG. 1 of the accompanying drawings. The amplifier 100 is comprised of a main differential amplifier 102 and a common mode amplifier 104 supplied by voltage signals Vcc and Vee. The main differential amplifier 102 also includes inputs for receiving an inverting and non-inverting input, differential inputs Vin.sup.- and Vin.sup.+. Also included in the main differential amplifier 102 are a bias port, ibias, for receiving a bias current, Idm, and an input port, Vcmin, for receiving a common mode control signal, or common mode feedback signal. The output signals of the main differential amplifier 102 are differential outputs Vo.sup.+ and Vo.sup.-.
The common mode amplifier 104 takes the differential outputs of the main differential amplifier 102, Vo.sup.+ and Vo.sup.-, and feeds them into input ports Vcmp and Vcmn respectively. The common mode amplifier 104 includes a bias port, icmbias, for receiving a current source Icm, and also has a reference port Vag for receiving a reference input voltage. Also included in the common mode amplifier 104 is a control output port, Vcontrol, coupled to the Vcmin port of the main differential amplifier 102.
The common mode output signal for the operational amplifier 100 is defined by (Vo.sup.+ +Vo.sup.-)/2. This common mode output signal can be undefined and cause the output of the op amp to drift from a high gain region to a low gain region. To prevent this condition, a form of common mode feedback is used in order to define and stabilize the common mode output signal. Also, it is desirable to have a settling time response in the common mode amplifier 104 that is fast enough to avoid slowing the settling time response of the main differential amplifier 102. The output voltage swing, Vd, of the fully differential op-amp 100 is determined by the differential output voltages, where Vd=Vo.sup.++-Vo.sup.-. The common mode voltage, Vcm, of the differential op-amp 100 is determined by the average of the differential output voltages, where Vcm=(Vo.sup.+ +Vo.sup.-)/2 with respect to a reference voltage, Vag. If the common mode voltage, Vcm, is continuously compared with a constant reference voltage, such as Vag=analog ground, then the common mode feedback circuit is referred to as a continuous time common mode feedback circuit, CTCMFB.
A typical fully differential CMOS op-amp with CTCMFB is shown in FIG. 2 as fully differential op-amp 200. The fully differential op-amp 200 is comprised of FET transistors and is supplied by supply inputs Vcc and Vee and includes differential inputs Vin.sup.+ and Vin.sup.-. The main differential amplifier is represented by section 206 shown biased by current source Idm in section 202. The common mode amplifier is comprised of transistors M3, M4, M5, M6, M7 and M10 and overlaps with part of the main differential amplifier 206 which includes M5, M6, M7, M8, M9, and M10. Thus common mode amplifier 204 is a part of the main differential amplifier 206.
The common mode feedback operates by fixing the gate voltage of transistors M5 and M6 to a bias voltage Vb1 and establishing similar currents I+Io/2 through the gates M5 and M6 thus establishing stable source voltages. Once the source voltages for M5 and M6 are stabilized, the drain-to-source voltage for transistors M3 and M4, Vds3 and Vds4, become fixed. The value of Vb1 is chosen such that both transistors M3 and M4 operate in their linear regions. Aspect ratios, channel width vs. channel length, for transistors M3 and M4, (W/L)3=(W/L)4, are selected such that the common mode voltage, Vcm, has a predetermined value, such as ground potential. If the common mode voltage varies, the resistance of transistors M3 and M4 will vary accordingly and force Vcm back to its predetermined value due to the negative feedback nature of the circuit. The output voltage swing of the common mode feedback scheme shown in FIG. 2 is determined by the excess saturation voltage, Vds.sub.sat, of the output transistors, M 9/M10 and M7/M8 and is very process sensitive. The disadvantages associated with typical common mode feedback schemes include the inability to use them in single low voltage power supply environments without severely limiting the output voltage swing, (Vo.sup.+ -Vo.sup.-), of the operational amplifier.
In another common mode feedback scheme (not shown), the common mode voltage, Vcm, is periodically refreshed to the common mode reference voltage, Vag, then the common mode feedback circuit is referred to as dynamic common mode feedback, DCMFB. For dual supply systems Vag=ground potential. In single supply low voltage applications, the DCMFB approach is preferred, to increase the output voltage swing and improve time response. However, DCMFB circuits are based on switched capacitor techniques and introduce additional switching noise to the output signal.
Other common mode amplifiers schemes include those designed with resistors. These amplifiers have problems in that resistor tolerances in CMOS are poorly controlled, and the large value resistors typically used in operational amplifier circuits degrade the performance of the amplifier by limiting the output voltage swing, thereby forcing operation at higher supply voltages where the limited voltage swing is not a disadvantage.
Hence, there is a need for a continuous time common mode feedback amplifier circuit suitable for low voltage single supply applications that provides a wide output voltage swing with fast transient response times.